Title :
Design of SDHC Card Video Player Based on SoPc
Author :
Yansi Yang ; Yingyun Yang ; Lipi Niu
Author_Institution :
Inf. Eng. Sch. Commun., Univ. of China, Beijing, China
Abstract :
This paper presents an SDHC card video player based on SoPC technology, which keeps abreast of the time and adopt an SDHC card as MPEG-2 video storage device. To achieve the high-speed MPEG-2 decode and real-time video display, NIOS II CPU are cooperated with IDCT hardware acceleration IP core, and two display buffer SRAMs are alternately utilized to guarantee continuous video data export.
Keywords :
SRAM chips; buffer storage; system-on-chip; video coding; video equipment; IDCT hardware acceleration IP core; MPEG-2 video storage device; NIOS II CPU; SDHC card video player design; SoPC technology; buffer SRAM; continuous video data export; high-speed MPEG-2 decode; real-time video display; system-on-a-programmable-chip; Decoding; Field programmable gate arrays; IP networks; Random access memory; Real-time systems; Streaming media; Transform coding; FPGA; IDCT; MPEG-2; SDHC; SoPC;
Conference_Titel :
Instrumentation, Measurement, Computer, Communication and Control (IMCCC), 2012 Second International Conference on
Conference_Location :
Harbin
Print_ISBN :
978-1-4673-5034-1
DOI :
10.1109/IMCCC.2012.216
