Power optimal partitioning for dynamically reconfigurable FPGA

To implement a circuit system on dynamically reconfigurable FPGAs (DRFPGAs), we must partition it into sub-circuits and execute each sub-circuit in order. Traditional partitioning methods focus on optimizing the number of communication buffers. In this paper, we study the partitioning problem targeting at power optimization for the DRFPGAs. We analyze the power consumption caused by the communication buffers in the partitioning. Then we transform a circuit system into the corresponding flow network and apply a flow-based algorithm to find the partitioning of optimal power consumption. Experimental results demonstrate the effectiveness of our method.