Comparative analysis of 10T and 14T full adder at 45nm technology

Adders are basic building block of Arithmetic VLSI circuits found in processors and microcontroller inside Arithmetic and Logic units. Upgrading the performance of the adder thus becomes imperative which would certainly result in the improvement of digital electronic circuits where adder is employed. Full adders, till now, have been designed using wide range of structures for improvement of various parameters like power consumption, speed performance and structure size. The paper here describes a comparative analysis of 10T and 14T full adder with the aim of increasing power efficiency and reducing structure size at 45nm technology. The simulation results have been obtained for power by varying different parameters using Cadence Virtuoso Tool and SPECTRE simulator.