On improving the performance of Traff´s comparator

Author

Sridhar, Rajeswari ; Pandey, Narendra ; Bhatia, Vandana ; Bhattacharyya, A.

Author_Institution

Dept. of Electron. & Commun. Eng., Delhi Technol. Univ., New Delhi, India

fYear

2012

fDate

6-8 Dec. 2012

Firstpage

1

Lastpage

4

Abstract

In this paper a new current comparator is proposed which offers high speed and high resolution while maintaining low power dissipation. The design improves upon previous Traff current comparator by modifying the given gain stage which leads to up to 83% improvement in delay. Simulation results performed on SPICE using TSMC 0.18μm CMOS technology demonstrate that proposed current comparator has a resolution of ± 10nA and delay of 0.86ns at ± 1μA input current. Performance for lower supply voltages is also reported.

Keywords

CMOS analogue integrated circuits; current comparators; SPICE; TSMC CMOS technology; Traff current comparator; gain stage; power dissipation; size 0.18 mum; time 0.86 ns; CMOS integrated circuits; Delay; Educational institutions; Inverters; Power supplies; Signal processing; Simulation; VLSI neural network; current comparator; current mode circuits; front end signal processing; function generation;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Electronics (IICPE), 2012 IEEE 5th India International Conference on

Conference_Location

Delhi

ISSN

2160-3162

Print_ISBN

978-1-4673-0931-8

Type

conf

DOI

10.1109/IICPE.2012.6450418

Filename

6450418