Title :
An enhanced current mirror for SSO simulation
Author_Institution :
Custom BU Package Design, Texas Instrum., Austin, TX, USA
Abstract :
Current mirrors are an established technique for reducing memory requirements and run time in Spice-based bus simulations with many simultaneously switching outputs (SSO). Mismatched delayss can reduce accuracy, and a current mirror bus architecture enhanced with a bridge circuit is shown to restore accuracy with mismatched package delays.
Keywords :
SPICE; bridge circuits; SSO simulation; Spice based bus simulation; bridge circuit; enhanced current mirror; memory requirements; mirror bus architecture; mismatched delays; mismatched package delays; switching outputs; Bridge circuits; Clocks; Data models; Delay; Jitter; Load modeling; Mirrors; SSI; SSN; SSO; Spice; bridge; current mirror;
Conference_Titel :
Electrical Performance of Electronic Packaging and Systems (EPEPS), 2012 IEEE 21st Conference on
Conference_Location :
Tempe, AZ
Print_ISBN :
978-1-4673-2539-4
Electronic_ISBN :
978-1-4673-2537-0
DOI :
10.1109/EPEPS.2012.6457858
