A Reconfigurable Parallel Prefix Ling Adder with modified Enhanced Flagged Binary logic

This paper presents a Reconfigurable Parallel Prefix Ling Adder. The proposed design can be partitioned to perform as one 16 bit, two 8 bit and four 4 bit adders. We also propose a new architecture for Enhanced Flagged Binary Adder (EFBA) designs which reduces the delay of operation considerably. The new adders are, therefore, modifications of conventional Reconfigurable Carry Lookahead Adder (CLA) - EFBA arrangements. We estimate a reduction of 6.8% in the delay in the critical path with respect to traditional implementation of CLA-EFBA logic. The proposed architectures are compared with the previous architectures in literature and are shown to perform better.