Variable input delay CMOS logic for dynamic IR drop reduction

A glitch compensation methodology is proposed in this paper which involves reducing the undesired switching of selected combinational cells from a place and routed standard cell layout in order reduce peak dynamic voltage or IR drop. The proposed methodology can be seamlessly integrated to existing physical design flow. A glitch is an undesired transition that occurs before intended value in digital circuits. A glitch occurs in CMOS circuits when differential delay at the inputs of a gate is greater than inertial delay, which results into notable amount of power consumption. The glitch power is becoming more prominent in lower technology nodes. Introduction of buffers at the input of the Logic gate may reduce glitches, but it results into large area overhead and dynamic power. Hence, the proposed methodology will ensure low dynamic power consumption with less area. The pass transistor logic is used as a compensation circuit and a flow is also proposed for characterizing the pass transistor logic to cater different delay values. The proposed methodology has been validated on a place and routed Multiply Accumulate (MAC) layout implemented using Synopsys SAED 90 nm Generic library. Experimental results show 12% to 50% reduction in peak transient IR drop numbers with just 12% reduction in glitch power. Also when compared to standard on-chip decoupling capacitor (Decap) cells insertion method which is used to minimize dynamic IR drop, the proposed method could achieve the same without contributing to extra leakage power.