DocumentCode :
594248
Title :
Low power low jitter phase locked loop for high speed clock generation
Author :
Singh, G.S. ; Singh, D. ; Moorthi, S.
Author_Institution :
Dept. of Electr. & Electron. Eng., Nat. Inst. of Technol., Tiruchirappalli, India
fYear :
2012
fDate :
5-7 Dec. 2012
Firstpage :
192
Lastpage :
196
Abstract :
Low power consumption is always desired for any electronic products today. CMOS technology is the most common process to make integrated-circuits. The work focuses on the design and simulation of low jitter and low power CMOS PLL integrated circuits using 180nm CMOS technology. A current-controlled ring oscillator based on a single-ended rail-to-rail operational transconductance amplifier (OTA) and three simple CMOS inverters, is employed and tested in this work. The circuit uses less number of transistors and hence consumes low power compared to conventional oscillator circuits. Conventional static Phase Frequency Detector (PFD) has a wide dead zone (undetectable phase difference range), which results in increased jitter. The jitter caused by the large dead zone can be reduced by increasing the precision of the phase frequency detector. Any width of the dead-zone directly translates to jitter in the PLL which is an undesirable performance that must be avoided. To overcome the speed limitation and to reduce the dead zone, a new dynamic logic style PFD was designed and simulated. The designing of charge pump for getting faithful response is a difficult task because of mismatch in charging and discharging currents. The charge pump developed in this work employs an operational amplifier designed for reducing the error caused by high speed glitches in the transistor and mismatch between charging and discharging currents. A low noise charge-pump to achieve low phase jitter together with OTA based VCO, a PFD based on dynamic logic circuit, and a passive loop filter is integrated to obtain the Phase Locked Loop architecture. The simulation results of the PLL exhibits a working frequency range of 640 to 800 MHz and the utmost lock time of 6s. This frequency range renders the designed phase locked loop architecture that can be used as clock generator in microprocessors.
Keywords :
CMOS integrated circuits; UHF integrated circuits; charge pump circuits; clocks; jitter; logic circuits; low-power electronics; operational amplifiers; phase detectors; phase locked loops; voltage-controlled oscillators; CMOS inverters; CMOS technology; OTA based VCO; PFD; charge pump design; charging currents; clock generator; current-controlled ring oscillator circuits; discharging currents; dynamic logic style PFD design; electronic products; frequency 640 MHz to 800 MHz; high speed clock generation; integrated-circuits; large dead zone; low power CMOS PLL integrated circuits; low power consumption; low power low jitter phase locked loop; microprocessors; phase locked loop architecture; single-ended rail-to-rail operational transconductance amplifier; size 180 nm; static phase frequency detector; time 6 ns; transistors; CMOS integrated circuits; Charge pumps; Jitter; Phase frequency detector; Phase locked loops; Voltage control; Voltage-controlled oscillators; OTA; PLL; charge-pump(CP); low-jitter; low-power;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microelectronics and Electronics (PrimeAsia), 2012 Asia Pacific Conference on Postgraduate Research in
Conference_Location :
Hyderabad
ISSN :
2159-2144
Print_ISBN :
978-1-4673-5065-5
Type :
conf
DOI :
10.1109/PrimeAsia.2012.6458652
Filename :
6458652
Link To Document :
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