Providing 100% throughput in memory-memory-memory switches with in-sequence service

The use of buffers in the central stage of memory-memory-memory (MMM) switch can potentially cause the forwarding of packets to the outputs in out-of-sequence order. In this study, the authors present a novel scheduling algorithm, frame-based in-sequence scheduling in MMM switch (FIM³), which can provide 100% throughput and in-sequence service as well. FIM³ adopts a predetermined cyclic shift configuration at the first stage and the oldest-cell-first selection for arbitrations at the second and third stages. Frame-based scheduling algorithm is adopted, and fake packets will be added for an incomplete frame to obtain full. FIM³ is decentralised and requires no speedup. The simulation results show that FIM³ has a better delay performance than padded frame does under uniform traffic, and achieves 100% throughput under non-uniform traffic.