• DocumentCode
    59534
  • Title

    237 Gbit/s unrolled hardware polar decoder

  • Author

    Giard, P. ; Sarkis, G. ; Thibeault, C. ; Gross, W.J.

  • Author_Institution
    Electr. & Comput. Eng. Dept., McGill Univ., Montreal, QC, Canada
  • Volume
    51
  • Issue
    10
  • fYear
    2015
  • fDate
    5 14 2015
  • Firstpage
    762
  • Lastpage
    763
  • Abstract
    A new architecture for a polar decoder using a reduced complexity successive-cancellation (SC) decoding algorithm is presented. This novel fully unrolled, deeply pipelined architecture is capable of achieving a coded throughput of over 237 Gbit/s for a (1024, 512) polar code implemented using a field-programmable gate array. This decoder is two orders of magnitude faster than state-of-the-art polar decoders.
  • Keywords
    decoding; field programmable gate arrays; FPGA; complexity successive cancellation; decoding algorithm; field programmable gate array; pipelined architecture; polar code; unrolled hardware polar decoder;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el.2014.4432
  • Filename
    7105452
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=59534