FPGA implementation of a three-way asynchronous DDR2 memory controller

This paper describes the implementation of a three-way asynchronous Double Data Rate (DDR2) memory controller using a Field-Programmable Gate Array (FPGA). The objective is to replace the memory buffer in a PC-based oscilloscope, where a First-In First-Out (FIFO) stack was used. The digital oscilloscope is used for measuring and reconstructing eye diagrams for high speed signals, such as Ethernet (1.25, 10.3125 Gbps), PCI-Express (2.5, 5.0, 6.125 Gbps), SATA (1.5, 3.0 Gbps), etc... Replacing the stack with DDR2, improves the quality of the eye diagram, which describes parameters of the input signal, for the DDR2 higher data transfer speed and larger memory size.