Title :
Multi-channel BER tester module based on FPGA
Author :
Meixia Duan ; Jinlin Zhuang
Author_Institution :
North China Univ. Of Water Conservancy & Electr. Power, Zhengzhou, China
Abstract :
This paper introduces a design and implementation of mulit_BER tester basing on FPGA. According the theory and method of error code generated and error code measured, the hardware platform is FPGA+ARM. Source simulation, recovery of the receive clock and synchronization of local sequence is implemented in the FPGA,. The feasibility of design method is proved by the verification of simulation and experiment in the field.
Keywords :
circuit testing; clocks; codes; error statistics; field programmable gate arrays; modules; synchronisation; ARM; FPGA; error code generation method; error code measurement; local sequence synchronization; multichannel BER tester module; receive clock recovery; Bit error rate; Educational institutions; Field programmable gate arrays; Graphics; Measurement uncertainty; Receivers; Synchronization;
Conference_Titel :
Advanced Computational Intelligence (ICACI), 2012 IEEE Fifth International Conference on
Conference_Location :
Nanjing
Print_ISBN :
978-1-4673-1743-6
DOI :
10.1109/ICACI.2012.6463359
