Second-order TDTL with initialization process

This paper proposes an improved time delay digital tanlock loop (TDTL) system in which a feedforward loop is used to initialize the loop filter memory so as to enhance the acquisition speed of the system. The feedforward loop is used to estimate the value of the steady-state frequency of the input signal which is subsequently loaded into the memory of the loop filter. The system was simulated and tested using Simulink/Matalb using frequency step and FSK modulation. Further, the system was implemented using an FPGA and testing results indicate an ample improvement in the acquisition speed over the original TDTL system.