DocumentCode
596809
Title
Towards AER VITE: Building spike gate signal
Author
Perez-Pena, Fernando ; Morgado-Estevez, Arturo ; Rioja-Del-Rio, C. ; Linares-Barranco, Alejandro ; Jimenez-Fernandez, A. ; Lopez-Coronado, J. ; Munoz-Lozano, J.L.
Author_Institution
Appl. Robot. Lab., Univ. of Cadiz, Cadiz, Spain
fYear
2012
fDate
9-12 Dec. 2012
Firstpage
881
Lastpage
884
Abstract
Neuromorphic engineers aim to mimic the precise and efficient mechanisms of the nervous system to process information using spikes from sensors to actuators. There are many available works that sense and process information in a spike-based way. But there are still several gaps in the actuation and motor control field in a spike-based way. Spike-based Proportional-Integrative-Derivative controllers (PID) are present in the literature. On the other hand, neuro-inspired control models as VITE (Vector Integration To End point) and FLETE (Factorization of muscle Length and muscle Tension) are also present in the literature. This paper presents another step toward the spike implementation of those neuro-inspired models. We present a spike-based ramp multiplier. VITE algorithm generates the way to achieve a final position targeted by a mobile robotic arm. The block presented is used as a gate for the way involved and it also puts the incoming movement on speed with a variable slope profile. Only spikes for information representation were used and the process is in real time. The software simulation based on Simulink and Xilinx System Generator shows the accurate adjust to the traditional processing for short time periods and the hardware tests confirm and extend the previous simulated results for any time. We have implemented the spikes generator, the ramp multiplier and the low pass filter into the Virtex-5 FPGA and connected this with an USB-AER (Address Event Representation) board to monitor the spikes.
Keywords
field programmable gate arrays; low-pass filters; mobile robots; neurocontrollers; three-term control; AER VITE; Simulink system generator; USB AER; VITE algorithm; Virtex 5 FPGA; Xilinx system generator; actuation; actuators; address event representation; hardware test; low pass filter; mobile robotic arm; motor control field; nervous system; neuro inspired control model; neuromorphic engineers; sensors; software simulation; spike based proportional integrative derivative controllers; spike based ramp multiplier; spike based way; spike gate signal; spikes generator; variable slope profile; Generators; Hardware; Neurons; Radiation detectors; Robots; Software;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits and Systems (ICECS), 2012 19th IEEE International Conference on
Conference_Location
Seville
Print_ISBN
978-1-4673-1261-5
Electronic_ISBN
978-1-4673-1259-2
Type
conf
DOI
10.1109/ICECS.2012.6463521
Filename
6463521
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