A dead-zone free and linearized digital PLL

This paper implements a novel digital solution to avoid the problem of dead-zone behavior in digital phase locked loop (DPLL) caused by the quantization effect of time-to-digital converter (TDC). The dead-zone behavior results in chaotic limit cycle behavior causing higher than expected in-band phase noise and strong spurious tones. This behavior is dependent on the initial phase difference between the output and reference clock which makes the DPLL performance inconsistent and unpredictable. To alleviate this problem, a noise shaped offset is added to the phase error, in the digital domain to keep the TDC active and away from the dead-zone. The proposed solution is verified by extensive simulation and using a DPLL prototype in a 0.13 μm CMOS process.