DocumentCode
596838
Title
Fast floorplanning for fixed-outline and nonrectangular regions
Author
Ahmed, Moataz A. ; Pinge, S. ; Chrzanowska-Jeske, Malgorzata
Author_Institution
Electr. & Comput. Eng., Portland State Univ., Portland, OR, USA
fYear
2012
fDate
9-12 Dec. 2012
Firstpage
464
Lastpage
467
Abstract
We present a fast evolutionary algorithm using sequence pair (SP) representation for hard block fixed-outline and non-rectangular floorplanning. We use dummy modules to represent various non-rectangular floorplans. The dummy module locations on layout and the feasibility of candidate solutions are verified directly on the SP representation without generating constraint graphs or floorplans. It significantly speeds up the algorithm. The developed fixed-outline floorplanner is fast and has a high success rate for hard block fixed-floorplans with dead spaces limited by 10%, 8% and 6%. It can also efficiently handle preplaced modules. Experimental results are presented.
Keywords
evolutionary computation; integrated circuit layout; dummy module locations; fast evolutionary algorithm; fast floorplanning; fixed-outline regions; hard block fixed-floorplans; hard block fixed-outline floorplanning; nonrectangular floorplanning; nonrectangular regions; sequence pair representation; Algorithm design and analysis; Benchmark testing; Evolutionary computation; Layout; Optimization; Shape; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits and Systems (ICECS), 2012 19th IEEE International Conference on
Conference_Location
Seville
Print_ISBN
978-1-4673-1261-5
Electronic_ISBN
978-1-4673-1259-2
Type
conf
DOI
10.1109/ICECS.2012.6463553
Filename
6463553
Link To Document