Title :
Dual-edge triggered sense amplifier flip-flop utilizing an improved scheme to reduce area, power, and complexity
Author :
Esmaeili, S.E. ; Islam, Rashed ; Al-Khalili, A.J. ; Cowan, Glenn E. R.
Author_Institution :
Electr. & Comput. Eng. Dept., Concordia Univ., Montreal, QC, Canada
Abstract :
In this paper, we propose a dual-edge sense amplifier flip-flop (DE-SAFF) using an improved clocking scheme to reduce area, power, and complexity. The proposed scheme does not require any changes on the single-edge flip-flop to enable dual-edge triggering. The extracted circuit layout of the proposed DE-SAFF has been simulated in TSMC 65-nm technology at a frequency of 2.5 GHz and a throughput of 5 GHz. Simulation results show correct functionality of the proposed flip-flop under process, voltage, and temperature (PVT) variations. Comparing the proposed DE-SAFF to other flip-flops, show that in addition to reduced design complexity, the proposed flip-flop has low power consumption and a lower area.
Keywords :
UHF amplifiers; amplifiers; flip-flops; integrated circuit layout; logic design; DE-SAFF; PVT variations; TSMC technology; area reduction; circuit layout; clocking scheme; design complexity; dual-edge triggered sense amplifier flip-flop; frequency 2.5 GHz; frequency 5 GHz; power consumption; process voltage and temperature variations; single-edge flip-flop; size 65 nm; Clocks; Delay; Flip-flops; Logic gates; Periodic structures; Power demand; Transistors;
Conference_Titel :
Electronics, Circuits and Systems (ICECS), 2012 19th IEEE International Conference on
Conference_Location :
Seville
Print_ISBN :
978-1-4673-1261-5
Electronic_ISBN :
978-1-4673-1259-2
DOI :
10.1109/ICECS.2012.6463565
