A novel multi-step C-2C DAC architecture

In this article, design of a novel DAC architecture is presented. This DAC can be utilized as part of a successive approximation register (SAR) ADCs or as a standalone unit in biomedical or wireless sensor network nodes. The DAC presented combines a multi-step methodology and a C-2C converter with a lower resolution than the main converter and four switches to produce the desired analog output signal. According to the proposed idea, an 8-bit DAC is designed, comprising a total capacitance of 11CUnit and 8 switches. The circuit was designed and simulated in a 0.18-μm standard CMOS technology with a supply voltage of 1.8V. Simulated INL of the DAC is in the range +0.42 LSB to -0.40 LSB and the DNL values are within the limit +0.6 LSB to -0.03 LSB.