Title :
Real-time FPGA connected component labeling system
Author :
Calvo-Gallego, E. ; Aldaya, A.C. ; Brox, Piedad ; Sanchez-Solano, Santiago
Author_Institution :
Dept. of Electron. & Electromagn., Univ. of Seville, Seville, Spain
Abstract :
The implementation of a connected component labeling algorithm (CCL) for real-time operation is presented in this paper. The algorithm, which was designed and implemented following a model-based methodology centered on Matlab/Simulink and Xilinx-System Generator, uses horizontal and vertical blanking periods to improve the quality of labeling and increase the operation speed. Its performance, with a VGA 640 × 480 P @ 60 Hz video, is shown by means of its integration on a complete video processing system over a Spartan-3A DSP 3400 development board.
Keywords :
digital signal processing chips; field programmable gate arrays; video signal processing; FPGA; Matlab/Simulink; Spartan-3A DSP 3400 development board; VGA; Xilinx-system generator; connected component labeling system; field programmable gate arrays; frequency 60 Hz; horizontal blanking periods; model-based methodology; vertical blanking periods; video processing system; Algorithm design and analysis; Blanking; Field programmable gate arrays; Image resolution; Labeling; Real-time systems; Software algorithms;
Conference_Titel :
Electronics, Circuits and Systems (ICECS), 2012 19th IEEE International Conference on
Conference_Location :
Seville
Print_ISBN :
978-1-4673-1261-5
Electronic_ISBN :
978-1-4673-1259-2
DOI :
10.1109/ICECS.2012.6463677
