DocumentCode
596976
Title
A low-power fully differential cyclic 9-bit ADC
Author
Bako, Niko ; Baric, Adrijan
Author_Institution
Univ. of Zagreb, Zagreb, Croatia
fYear
2012
fDate
9-12 Dec. 2012
Firstpage
504
Lastpage
507
Abstract
This paper describes a low-power fully differential cyclic ADC. It utilizes a 4-bit binary weighted capacitor array to obtain 9-bit resolution. The operational amplifier with the slew rate detection is used to increase the speed of the ADC. The simulated power consumption of the ADC is 7.4 μW@1.4 V at the sampling rate of 10 kS/s. The simulated DNL and INL are 0.1/-0.18 LSB and 0.22/-0.2 LSB respectively. The results are based on post-layout simulations.
Keywords
analogue-digital conversion; differential amplifiers; operational amplifiers; analog-digital converter; binary weighted capacitor array; fully differential cyclic ADC; low power ADC; operational amplifier; post layout simulation; power 7.4 muW; slew rate detection; voltage 1.4 V; Capacitors; Latches; Noise; Operational amplifiers; Power demand; Radiofrequency identification; Transistors;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits and Systems (ICECS), 2012 19th IEEE International Conference on
Conference_Location
Seville
Print_ISBN
978-1-4673-1261-5
Electronic_ISBN
978-1-4673-1259-2
Type
conf
DOI
10.1109/ICECS.2012.6463698
Filename
6463698
Link To Document