A formal framework for testing with assertion checkers in mixed-signal simulation

Improving design methodologies for mixed-signal circuits raises many challenges, among them testing that the expected behavior is respected. We focus here on Assertion-Based Verification, performed thanks to automatically constructed assertion checkers (monitors): the circuit specification is formalized as logic and temporal properties, that are transformed into hardware checkers. These components, connected to the design under verification (DUV), can check at runtime (i.e., during simulation or FPGA emulation) that the DUV conforms to the assertions. The purpose of this paper is the adaptation to mixed-signal systems of such an assertion-based testing method for digital circuits. We propose a semantic analysis of the simulation context and a formal framework to support the reuse of assertion checkers in mixed-signal simulation.