Accurate estimation of analog test metrics with extreme circuits

Specification-based testing of analog/RF circuits is very costly due to lengthy test times and highly sophisticated test equipment. Alternative test measures, extracted by means of Built-In Test (BIT) techniques, are a promising approach to replace standard specification-based tests. However, these test measures must be evaluated at the design stage, before the real production, by estimating parametric test errors such as Test Escapes (T_E) and Yield Loss (Y_L). An accurate estimation of these metrics requires a large non-biased sample of circuit instances including parametric defective ones. Since these extreme circuits are rare events, they cannot be obtained with a Monte Carlo simulation of an affordable size. However, statistical learning techniques, in combination with Monte Carlo simulation, can allow the generation of such a sample for multivariate test metrics estimation. In this paper, we will demonstrate this technique for the evaluation of an RF LNA BIT technique for which a large database of 10⁶ circuits has been simulated for comparison purposes.