Self-biased input common-mode generation for improving dynamic range and yield in inverter-based filters

Author

Gines, A.J. ; Villegas, A. ; Peralias, E. ; Rueda, Andrea

Author_Institution

Inst. de Microelectron. de Sevilla, Univ. of Seville, Sevilla, Spain

fYear

2012

fDate

9-12 Dec. 2012

Firstpage

256

Lastpage

259

Abstract

A simple and robust circuit for the input commonmode voltage generation in CMOS pseudo-differential inverter-based transconductors is proposed. The solution can improve the in-band IIP₃ in 7.8dBV_p and the 1-dB compression point in 5.3dBV_p compared to conventional approaches, with less noise, power consumption and occupied die area. A 1.2V 3.42mW 1.3-3.7MHz high-linear 8^th order bandpass complex filter is presented as demonstrator in a CMOS 90nm process. The yield for an image rejection ration IRR above 50dB is 86%, which represents a 31% improvement respect to the classical approach.

Keywords

CMOS logic circuits; band-pass filters; logic gates; CMOS pseudodifferential inverter-based transconductors; compression point; die area; dynamic range improvement; frequency 1.3 MHz to 3.7 MHz; high-linear 8-order bandpass complex filter; image rejection ration; in-band IIP₃; inverter-based filters; power 3.42 mW; power consumption; robust circuit; self-biased input common-mode generation; size 90 nm; voltage 1.2 V; yield improvement; Band pass filters; Bandwidth; CMOS integrated circuits; Inverters; Linearity; Noise; Robustness; CMOS pseudo-differential inverter-based transconductors; bandpass complex filter;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems (ICECS), 2012 19th IEEE International Conference on

Conference_Location

Seville

Print_ISBN

978-1-4673-1261-5

Electronic_ISBN

978-1-4673-1259-2

Type

conf

DOI

10.1109/ICECS.2012.6463752

Filename

6463752