Performance evaluation of RAM-based implementation of Finite State Machines in FPGAs

Author

Senhadji-Navarro, R. ; Garcia-Vargas, I. ; Guisado, J.L.

Author_Institution

Dipt. de Arquitectura y Tecnol. de Comput., Univ. de Sevilla, Sevilla, Spain

fYear

2012

fDate

9-12 Dec. 2012

Firstpage

225

Lastpage

228

Abstract

This paper presents a study of performance of RAM-based implementations in FPGAs of Finite State Machines (FSMs). The influence of the FSM characteristics on speed and area has been studied, taking into account the particular features of different FPGA families, like the size of LUTs, the size of memory blocks, the number of embedded multiplexer levels and the specific decoding logic for distributed RAM. Our study can be useful for efficiently implementing FPGA-based state machines.

Keywords

field programmable gate arrays; finite state machines; performance evaluation; random-access storage; FPGA families; FSM characteristics; LUT; distributed RAM; embedded multiplexer levels; finite state machines; memory blocks; performance evaluation; specific decoding logic; Decoding; Encoding; Field programmable gate arrays; Memory management; Multiplexing; Random access memory; Table lookup;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems (ICECS), 2012 19th IEEE International Conference on

Conference_Location

Seville

Print_ISBN

978-1-4673-1261-5

Electronic_ISBN

978-1-4673-1259-2

Type

conf

DOI

10.1109/ICECS.2012.6463760

Filename

6463760

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=597036