FPGA implementation of very high radix square root with prescaling

In this paper we investigate the implementation of a very high radix square root unit with prescaling on a modern FPGA. A parameterized sequential architecture has been implemented for Xilinx Spartan-6 devices. It relies on a specially handcrafted multiply-accumulate (MAC) unit implemented with DSP48A1 slices in order to perform multiply and multiply-add operations required by the algorithm. The proposed scheme uses all the features of Spartan-6 DSP slice: pre-adders, 18×18 bits multiplier and the post-adders. The MAC unit takes advantage of the limited size of one of the operands. Therefore, a small number of DSP blocks is used, which increases linearly with the operand size. Results show that implementations for high precision numbers (quad) are favored in terms of performance.