Gate-level modeling for CMOS circuit simulation with ultimate FinFETs

With the high complexity of current digital circuits, the use of gate-level models during the design process is mandatory. For standard CMOS technologies, designers assemble standard cells for which the gate-level model is provided by the founderies. For a given technology, the temporal parameters (such as propagation delays) are constants that can be extracted from experimental measurements. For FinFET-based circuits, such standard cells do not exist. As a consequence, to get predictive simulations of a circuit, the use of low-level model is required. To overcome this problem, we develop a predictive gate-level model for such circuits. To feed the timing parameters of the models, an automated procedure is established. It is based on a new compact model for ultimate FinFET mostly based on physical equations we recently develop. The results obtained with both approaches (compact model and gate-level model) are compared in the last part of the paper. For a digital circuit with about 80 transistors, the results are in accordance. The slight inaccuracy of the gate-level model is largely compensated by a very short simulation time.