A method to make SoC verification independent of pin multiplexing change

As the size and complexity of System-On-Chip (SoC) design is increasing rapidly, a portable and structured verification (testbench) environment is desired to cope with time to market. The pin multiplexing complexity i.e number of functions/peripherals (IPs) multiplexed on a single I/O pad is growing rapidly as many functions/IPs are getting integrated into single device. There are SoCs where four or more functions/peripherals are multiplexed on a single chip pad as the application usage of each IP/function is mutually exclusive in nature. This pin multiplexing option changes across SoCs and also in between different releases for the same SoC. Over time, it is being observed that this I/O pad multiplexing becomes major bottleneck in reusing/porting/creating testbench and verification environment across SoCs and releases. In this paper, we are proposing a new testbench layer (i.e “Function mapping”) in between the device under verification(DUV) and the various testbench components (e.g testbench drivers/ testbench monitors/bus functional models). This new layer reduces the overall verification cycle time significantly (approx 20% to 50%). We will discuss this layer implementation and usage in detail and results of the proposed approach.