Compression and decompression of FPGA bitstreams

Reconfigurable system uses bitstream compression to reduce the bitstream size and the memory requirement. The communication bandwidth is improved by reducing the reconfiguration time. Existing research has explored efficient compression with slow decompression or fast decompression at the cost of compression efficiency. This paper proposes a decode-aware compression technique to improve both compression and decompression efficiencies. The three major contributions of this paper are: i) Efficient bitmask selection technique that can create a large set of matching patterns; ii) Proposes a bitmask based compression using the bitmask and dictionary selection technique that can significantly reduce the memory requirement iii) Efficient combination of bitmask-based compression and run length encoding of repetitive patterns. The original bitstream can be generated using the decompression engine.