Performance and reliability of a 65nm Flash based FPGA

Author

Jia, J.Y. ; Singaraju, Pavan ; Dhaoui, Fethi ; Newell, R. ; Liu, Peng ; Micael, H. ; Traas, M. ; Sammie, S. ; Hawley, Frank ; McCollum, John ; Van den Abeelen, Werner

Author_Institution

Microsemi Corp., San Jose, CA, USA

fYear

2012

fDate

Oct. 29 2012-Nov. 1 2012

Firstpage

1

Lastpage

3

Abstract

We present a highly reliable Flash based FPGA fabricated with a 65nm embedded process. A very robust ON and OFF Vt window, over 8V, has been achieved with tight cell to cell distributions. 1k program/erase cycles have been performed and charge trap induced Vt window loss is less than 0.2V. Some initial Vt shift is seen at erase side after retention bake. The shift saturates after 24 hours and the post-bake Vt window is close to 8V. There is still a 2V margin from our design spec which is 6V. Operation disturb life time was extrapolated from an accelerated test. AC life time is greater than 2000 years. For some high security applications we provide a user-verify feature. Based on accelerated testing we have proposed the number of user verifies and predicted the error rate.

Keywords

circuit reliability; embedded systems; field programmable gate arrays; flash memories; life testing; accelerated testing; charge trap; embedded process; error rate prediction; extrapolation; flash based FPGA; program-erase cycle; reliability; retention bake; robust OFF Vt window; robust ON Vt window; security application; size 65 nm; tight cell to cell distribution; time 24 hour; voltage 2 V; voltage 6 V; Arrays; Degradation; Error analysis; Field programmable gate arrays; Hot carriers; Life estimation; Logic gates;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on

Conference_Location

Xi´an

Print_ISBN

978-1-4673-2474-8

Type

conf

DOI

10.1109/ICSICT.2012.6466679

Filename

6466679