Title :
Si Nanowire tunnel FETs with epitaxial NiSi2 source/drain and dopant segregation
Author :
Knoll, Lars ; Zhao, Q.T. ; Richter, Simon ; Trellenkamp, Stefan ; Schafer, Andreas ; Bourdelle, Konstantin K. ; Mantl, Siegfried
Author_Institution :
Peter Grunberg Inst. 9 (PGI 9), Forschungszentrum Julich, Julich, Germany
fDate :
Oct. 29 2012-Nov. 1 2012
Abstract :
Si Nanowire (NW) TFETs with a NW cross section of 30×7nm2 were fabricated on ultra thin SOI. Implanattion into epitaxial NiSi2 silicide (IIS) source and drain and a subsequent anneal at low temperatures for dopant segregation (DS) were used for formation of junctions. Si NW Schottky MOSFETs with dopant segregated NiSi2 source/drain showed very low Schottly barrier, which demonstrates a high concentration of dopants segregated at the NiSi2 edges even after low temperature anneals. Tilted dopant implantation using the gate as a shadow mask allows self-aligned formation of p-i-n tunneling FETs. The steep junctions fromed at low temperature improve the band-to-band tunneling. P-channel TFETs showed high on-currents (ION) of 18.8 μA/μm, very low off-currents (IOFF) and a large ION/IOFF ratio up to 108.
Keywords :
MOSFET; Schottky barriers; Schottky gate field effect transistors; annealing; elemental semiconductors; ion implantation; masks; nanowires; nickel compounds; semiconductor epitaxial layers; silicon; silicon-on-insulator; tunnelling; DS; NW; NW Schottky MOSFET; Schottly barrier; Si-NiSi2; annealing; band-to-band tunneling; dopant segregation; epitaxial source-drain; gate shadow mask; nanowire tunnel FET; p-channel TFET; p-i-n tunneling FET; self-aligned formation; steep junction; tilted dopant implantation; ultrathin SOI; Epitaxial growth; Junctions; Logic gates; MOSFETs; Silicides; Silicon; Tunneling;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on
Conference_Location :
Xi´an
Print_ISBN :
978-1-4673-2474-8
DOI :
10.1109/ICSICT.2012.6466720
