• DocumentCode
    597837
  • Title

    Study of reliability in superjunction power VDMOSFET

  • Author

    Zeng-Yi Fan ; Zheng-Yu Chu ; Jing Luo ; Gang Cao ; Liao, Shengcai

  • Author_Institution
    Dept. of Reliability Eng., Shanghai Hua Hong NEC Electron. Co. Ltd., Shanghai, China
  • fYear
    2012
  • fDate
    Oct. 29 2012-Nov. 1 2012
  • Firstpage
    1
  • Lastpage
    3
  • Abstract
    Comparing with CoolMOSTM, a new deep trench structure of superjunction power VDMOS has been developed in HHNEC. In this paper, we have studied main reliability failure mechanisms subjected to HTRB (High Temperature Reverse Bias). Positive improvement actions from both process and package assembly were showed.
  • Keywords
    assembling; power MOSFET; semiconductor device packaging; semiconductor device reliability; CoolMOSTM; HHNEC; HTRB; deep trench structure; high temperature reverse bias; package assembly; process assembly; reliability failure mechanism; superjunction power VDMOSFET; Assembly; Degradation; Failure analysis; MOSFETs; Optimization; Passivation; Reliability;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on
  • Conference_Location
    Xi´an
  • Print_ISBN
    978-1-4673-2474-8
  • Type

    conf

  • DOI
    10.1109/ICSICT.2012.6466724
  • Filename
    6466724
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=597837