A transport stream decoder subsystem design with a dedicated processor

In this paper, a flexible and low power transport stream decoding subsystem (named TP-DEC), accelerated by a dedicated transport processor (named DTP), is proposed. The TP-DEC is used for stream decoding, multi-channel routing configuration, transport de-multiplexing, hybrid ways of decryption/encryption, multi-channel pipeline PID filtering, etc. In order not to interrupt the main processor, the DTP is utilized to execute to match function on the stream data and to perform many general computing tasks. The DTP, a scalar RISC structure processor, has 3-stage pipeline, supports 16 bits wide instruction, and support data/instruction pre-fetch and caching function.