Title :
High voltage SJ-LDMOS with charge-balanced pillar and N− buffer layer
Author :
Wei Wu ; Bo Zhang ; Jian Fang ; Zhaoji Li
Author_Institution :
Sch. of Microelectron. & Solid State Electron., Univ. of Electron. Sci. & Technol. of China, Chengdu, China
fDate :
Oct. 29 2012-Nov. 1 2012
Abstract :
A novel SJ-LDMOS using charge-balanced pillar and N- buffer layer (CBB) is proposed. The charge-balanced pillars which provide additional charges for compensating a surplus of p-type charges around the drain end insure the charge balance and eliminate the substrate assisted depletion effect. In addition, the N- buffer layer under SJ region enables CBB SJ-LDMOS to use shallow pillars. Therefore the CBB SJ-LDMOS is compatible with CMOS technology. Simulation results indicate that the surface lateral electric field of the CBB SJ-LDMOS reaches 23.3V/μm, resulting in a breakdown voltage (BV) of 350V with 15μm drift length.
Keywords :
CMOS integrated circuits; MOSFET; buffer circuits; buffer layers; electric breakdown; BV; CBB; N- buffer layer; breakdown voltage; high voltage SJ-LDMOS; lateral double-diffusion MOSFET; p-type charge-balanced pillar; size 15 mum; substrate assisted depletion effect elimination; surface lateral electric field; voltage 350 V; Buffer layers; CMOS integrated circuits; CMOS technology; Electric fields; Geometry; Simulation; Substrates;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on
Conference_Location :
Xi´an
Print_ISBN :
978-1-4673-2474-8
DOI :
10.1109/ICSICT.2012.6467702
