Title :
DANoC: A dynamic adaptive Network on Chip architecture
Author :
Hao Shu ; Jiang-Yi Shi ; Yue Hao ; Pei-Jun Ma ; Zhao Xu
Author_Institution :
Key Lab. of Wide Band-gap Semicond. Mater. & Devices of Minist. of Educ., Xidian Univ., Xi´an, China
fDate :
Oct. 29 2012-Nov. 1 2012
Abstract :
Network-on-Chip has became a mainstream technology to solve the communication problems in Multi Processor SoC (MPSoC); and it has a greatly impact on system´s performance, area and power consumption. In order to improve the performance of Network-on-Chip to fulfill the requirements of the MPSoC, this paper presents a dynamic adaptive NoC (DANoC) architecture, which can achieve the topology dynamic adaptation at run time. There are many features of DANoC, such as: the topology is simple and regular; the architecture is easy to extend in different network scales; the network traffic load is balanced. DANoC and Mesh have been verified under different network scales, injection rates and traffic patterns. The experimental results show that DANoC could effectively reduce latency and improve throughput, which is a simple and efficient Network-on-Chip.
Keywords :
multiprocessing systems; network topology; network-on-chip; DANoC; MPSoC; dynamic adaptive network-on-chip architecture; injection rate; multiprocessor SoC; network scale; network traffic load; topology dynamic adaptation; traffic pattern; Computer architecture; Network topology; Ports (Computers); Routing; Throughput; Tiles; Topology;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on
Conference_Location :
Xi´an
Print_ISBN :
978-1-4673-2474-8
DOI :
10.1109/ICSICT.2012.6467768