Title :
High k/III-V structures: Interfaces, oxides quality and down scaling
Author :
Hai-Dang Trinh ; Chang, Edward Yi
Author_Institution :
Dept. of Mater. Sci. & Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fDate :
Oct. 29 2012-Nov. 1 2012
Abstract :
In this paper, we present our studies on high k/InGaAs and high k/InSb structures, focusing on the interfaces, oxides qualities as well as down scaling the gate oxide. We indicate the free movement of Fermi level in both kinds of n- and p-InGaAs MOSCAPs. The effect of gases plasma treatments in the improvement of gate oxides as well as high k/InGaAs interface quality is also discussed. For high k/InSb structure, the effect of post deposition annealing temperatures on electrical properties of this structure is presented. Finally, we present our efforts on down scaling the equivalent oxide thickness of these structures into sub-nm size.
Keywords :
Fermi level; III-V semiconductors; MOS capacitors; annealing; gallium arsenide; high-k dielectric thin films; indium compounds; nanoelectronics; plasma deposition; Fermi level; InGaAs; InSb; down scaling; electrical properties; equivalent oxide thickness; gases plasma treatments; gate oxide; high k-III-V structures; interface quality; n-MOSCAP; oxides quality; p-MOSCAP; post deposition annealing temperatures; Aluminum oxide; Capacitance; Capacitance-voltage characteristics; High K dielectric materials; Indium gallium arsenide; Logic gates; Plasmas;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on
Conference_Location :
Xi´an
Print_ISBN :
978-1-4673-2474-8
DOI :
10.1109/ICSICT.2012.6467799