Critical area-constrained redundant via insertion

Nowadays, redundant via insertion is the typical method to reduce the yield loss due to via failure. However, inserting a redundant via adjacent to a single via can create extra critical area between nets and worsen the reliability of the VLSI design. In this paper, we propose a critical area-constrained redundant via insertion method for yield optimization, which defines both double via and rectangle via as redundant via. Our method is the first to consider the critical area between nets during the redundant via insertion. The experiment results show that under different extract critical area constraint, the redundant via insertion rate declines in varying degrees. When we choose 10% extract critical area constrain between nets, the total redundant via insertion rate declines from 92.45% to 80.74% in MIS-based method, while our proposed method can obtain the similar insertion rate 91.88% for the tested circuits.