A low-power clock generator based on digital DLL for high speed pipelined ADCs

Author

Jun Cheng ; Liang Si ; Hong Zhang ; Xunwei Weng ; Zhenhai Chen ; Zhenjia Pu

Author_Institution

Sch. of Electron. & Inf. Eng., Xi´an Jiaotong Univ., Xi´an, China

fYear

2012

fDate

Oct. 29 2012-Nov. 1 2012

Firstpage

1

Lastpage

3

Abstract

This paper presents a low-power clock generator based on digital delay locked loop (DLL) for high-speed and high-resolution analog-to-digital converters (ADCs). A novel structure for the phase detector and delay controller is adopted to eliminate dithering and false locking of the DLL. The operation frequency range of the DLL is 30MHz~250MHz, and the corresponding locking time is about 66.4us and 730ns, respectively. The proposed clock generator consumes 7.7mW from a 1.8-V power supply. A 250MSPS, 10-bit charge domain pipelined ADC adopting the DLL is fabricated in SMC 0.18μm CMOS process and achieves a SNDR of 56.7 dB.

Keywords

CMOS integrated circuits; analogue-digital conversion; clocks; delay lock loops; CMOS process; DLL; SMIC; SNDR; delay controller; digital DLL; digital delay locked loop; frequency 30 MHz to 250 MHz; gain 56.7 dB; high speed pipelined ADC; high-resolution analog-to-digital converter; low-power clock generator; phase detector; power 7.7 mW; size 0.18 mum; voltage 1.8 V; word length 10 bit; Capacitors; Clocks; Delay; Generators; Inverters; Power supplies; Radiation detectors;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on

Conference_Location

Xi´an

Print_ISBN

978-1-4673-2474-8

Type

conf

DOI

10.1109/ICSICT.2012.6467900

Filename

6467900