A 0.3∼17.2GHz frequency divider with capacitive degeneration in 130nm CMOS

Author

Hanchao Zhou ; Wei Li ; Yangyang Niu ; Zibo Zhou ; Ning Li ; Junyan Ren

Author_Institution

State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China

fYear

2012

fDate

Oct. 29 2012-Nov. 1 2012

Firstpage

1

Lastpage

3

Abstract

A high speed and wide range CML frequency divider was realized in 130nm CMOS by using the capacitive degeneration technique. Varactors are placed at the source of the cross-coupled transistors to improve the self-oscillation frequency of dividers. With the tuning of varactors and PMOS load, wide range can be realized. When working at 1.2V supply voltage, a maximum locking range of 16.9 GHz, from the incident frequency 0.3 to 17.2 GHz, is achieved at the incident power of 0 dBm. The frequency divider consumes a static current of 3.6 mA.

Keywords

CMOS integrated circuits; UHF integrated circuits; current-mode logic; field effect MMIC; frequency dividers; microwave integrated circuits; varactors; CMOS; PMOS load; capacitive degeneration; cross-coupled transistors; current 3.6 mA; frequency 0.3 GHz to 17.2 GHz; high speed CML frequency divider; self-oscillation frequency; size 130 nm; static current; varactors; voltage 1.2 V; wide range CML frequency divider; CMOS integrated circuits; Frequency conversion; Phase locked loops; Transistors; Tuning; Varactors; capacitive degeneration; frequency divider; high speed; wide working range;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on

Conference_Location

Xi´an

Print_ISBN

978-1-4673-2474-8

Type

conf

DOI

10.1109/ICSICT.2012.6467910

Filename

6467910