• DocumentCode
    59845
  • Title

    Charge-Plasma Based Process Variation Immune Junctionless Transistor

  • Author

    Sahu, Chitrakant ; Singh, Jaskirat

  • Author_Institution
    Dept. of Electron. & Commun. Eng., Pandit Dwarka Prasad Mishra Indian Inst. of Inf. Technol. Design & Manuf., Jabalpur, India
  • Volume
    35
  • Issue
    3
  • fYear
    2014
  • fDate
    Mar-14
  • Firstpage
    411
  • Lastpage
    413
  • Abstract
    In this letter, we report for the first time a distinctive approach of implementing a junctionless transistor (JLT) without doping (doping-less) the ultrathin silicon film. A charge-plasma concept is employed to induce n-region for the formation of source and drain for a n-channel JLT using appropriate metal work function electrodes. Electrical characteristics of the proposed device are simulated and compared with that of a conventionally doped JLT of identical dimensions. In conventional JLTs, the channel doping concentration is generally kept high to ensure high ON-state current, but it causes variation in threshold voltage, which may be due to process variations. The proposed device solves the problem of threshold voltage variability without affecting inherent advantages of JLTs.
  • Keywords
    elemental semiconductors; semiconductor doping; silicon; technology CAD (electronics); thin film transistors; ON-state current; Si; channel doping concentration; charge-plasma concept; electrical characteristics; junctionless transistor; metal work function electrodes; n-channel JLT; n-region; threshold voltage variability; ultrathin silicon film; Doping; Logic gates; Metals; Semiconductor process modeling; Silicon; Transistors; Charge-plasma; TCAD; doping-less; random dopant fluctuation (RDF); sensitivity; simulation; variability;
  • fLanguage
    English
  • Journal_Title
    Electron Device Letters, IEEE
  • Publisher
    ieee
  • ISSN
    0741-3106
  • Type

    jour

  • DOI
    10.1109/LED.2013.2297451
  • Filename
    6712062