NBTI and dynamic variability in highly-scaled planar and gate-all-around MOSFETs

Summary form only given. As planar devices downscaling into nanometer region and going to the non-planar multiple-gate architecture for ultimately scaled CMOS technology, NBTI, as one of the key device reliability behavior, exhibits some different features. First we discuss NBTI induced dynamic variability issues in scaled devices. In addition to conventional time-dependent device-to-device variation (DDV) during NBTI degradation, a new source of cycle-to-cycle variation (CCV) due to the random occupation of trap states in each operation cycle is reported, including the characterization scheme, new observations, DC vs. AC NBTI effects and the frequency dependence of dynamic variation. On the other hand, NBTI behavior of the gate-all-around(GAA) Si nanowire transistors (SNWT), which is considered as one promising candidate for ultimate scaling, is also discussed, including the intrinsic (average) NBTI behavior in SNWTs with fast initial degradation, quick degradation saturation and special recovery behavior, as well as statistical NBTI behavior with the NBTI fluctuations in short-channel SNWTs, the enhanced single/few-trap behavior and large amplitude of stochastic degradation in SNWTs.