Chip-package-PCB thermal co-design for hot spot analysis in SoC

A chip-package-PCB thermal co-design methodology for system-on-chip (SoC) is proposed, and both simulation result and experiment data are presented. With the proposed methodology, it becomes feasible to address the hot spot issue which is an unfavourable but common thermal phenomenon existing in a highly integrated SoC as higher performance brings more power. To accurately model the hot spot of SoC, it´s prerequisite to capture the insights on the power distribution across the whole chip therefore SoC´s power map setting as heat source in computational-fluid-dynamics (CFD) model is defined. Furthermore, to realize exact local thermal effect on die level, detail 3-D flip chip package model, as well as detail PCB model based on trace-routing, are established. It was found that hot spot is an intrinsic consequence of the high power macro in SoC and only through optimization early in chip-package-PCB co-design phase is it possible to alleviate hot spot phenomenon. The proposed co-design methodology is particularly suited for BGA type package such as flip chip chip-scale-package (FCCSP), which is adopted commonly in mobile application processor. It´s shown that TV-1 and TV-2 simulation result is in consistency with experimental data in a 2-step validation therefore the effectiveness of this methodology is validated. In the example of design practice, we exercised this methodology to improve thermal performance by the adoption of patented copper pillar structure which shall be beneficial for flip chip package in general and without adding extra BOM cost or requiring additional effort/time on package qualification. The patented copper pillar bump design which can not only provide 4.1% performance gain compared to lead-free solder bump but will continue to be compatible in advance bump pitch for future wafer node.