Implementation of spectral subtraction method on FPGA using high-level programming tool

This paper presents a real-time architecture of spectral subtraction technique applied to speech enhancement. The proposed architecture is easily and quickly implemented on Field Programmable Gate Array (FPGA) using high-level programming tool in MATLAB/SIMULINK environment. Speech enhancement results obtained with fixed-point format implementation are compared to those obtained with the floating-point format one. The maximum operating frequency and resource utilization are presented for a Virtex-6 FPGA chip.