Design and simulation methodology for switch-cap circuits used in data converter applications

This paper provides a full methodological approach to designing and verifying differential sample and hold switched-capacitor circuits used in A/D converters. It provides a step-by-step process for translating system requirements such as signal-to-noise ratio (SNR) and sampling frequency into A/D requirements and subsequently into op-amp specifications. It also includes the design process of a switched-capacitor common mode feedback circuit (CMFB) to control the common mode output voltage. Furthermore, this paper provides practical methods for verifying the stability of the system. A design and simulation example for a differential sample and hold switched-capacitor circuit operating in a system requiring 5 MHz sampling frequency and a 6-bit A/D converter is provided. Mentor Graphics CAD tools were used in the design and simulations process using 180nm CMOS device models. This paper can be used as a resource for design engineers in the industry as well as universities teaching graduate level advanced electronics and data converter courses.