Design of a double AES processor

Advanced Encryption Standard (AES) is now widely used in different kinds of applications in software and hardware implementations. This paper presents the design and simulation of a double AES processor to explore the performance matrixes such as logic gates, speed and cost for the next generation IT security. Design of both Encryption and Decryption modules are carried out and simulated in an iterative design approach to minimize the hardware consumption. Here the operation like substitution bytes, mix column are simplified to reduce complexity and to produce a simple design which would deliver a high throughput and minimum latency.