Design and performance evaluation of a redundant binary full adder for uniform timing delay

Concurrency and timing guarantee are critical for robust performance of cyber-physical systems (CPS). Traditional binary adders are unable to provide such guarantee, as the timing delay is dependant on bit width and data. We present a design of a redundant binary full adder towards resolving this challenge, and a performance evaluation by implementing it with 0.6 μm CMOS technology. The design composes of three modules: binary-to-sign conversion, plus-plus-minus (PPM) adder and sign-to-binary conversion. The complete adder circuit was functionally verified using Virtuoso simulation, and the timing delays were compared with the conventional full adder circuits. Through Logical Effort optimization, 5 ns of the timing delay for PPM adder was achieved, which was constant for any bit width and independent of data. The design achieves reduced timing delay compared to common full adder circuits for 32-bit or higher number of bits. The design might be an attractive solution to provide uniform timing delay towards the CPS challenge.