Optimization of VLSI architectures for DTW

Author

Hussain, Shah Muhammed Abid ; Rashid, A.B.M.H.

Author_Institution

Dept. of Electr. & Electron. Eng., Bangladesh Univ. of Eng. & Technol., Dhaka, Bangladesh

fYear

2012

fDate

20-22 Dec. 2012

Firstpage

737

Lastpage

740

Abstract

In data mining and time series recognition applications Dynamic Time Warping (DTW) is a very popular method. It can produce accurate results provided its originality is preserved. But its lethargic nature has been inspiring development of its hardware based acceleration methods. In this paper, four novel VLSI architectures for performing DTW are proposed and compared. The comparison reflects achievement of significant conclusions specifically for performance critical and memory constraint applications.

Keywords

VLSI; field programmable gate arrays; DTW; FPGA; VLSI architecture optimization; data mining application; dynamic time warping; hardware-based acceleration method; time series recognition application; Algorithm design and analysis; Clocks; Computer architecture; Field programmable gate arrays; Heuristic algorithms; Random access memory; Very large scale integration; DTW; FPGA; VLSI; accelerator architectures; hardware implementation;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical & Computer Engineering (ICECE), 2012 7th International Conference on

Conference_Location

Dhaka

Print_ISBN

978-1-4673-1434-3

Type

conf

DOI

10.1109/ICECE.2012.6471656

Filename

6471656

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=599765