Performance and Power Solutions for Caches Using 8T SRAM Cells

Voltage scaling can reduce power dissipation significantly. SRAM cells (which are traditionally implemented using six-transistor cells) can limit voltage scaling due to stability concerns. Eight-transistor (8T) cells were proposed to enhance cell stability under voltage scaling. 8T cells, however, suffer from costly write operations caused by the column selection issue. Previous work has proposed Read-Modify-Write (RMW) to address this issue at the expense of an increase in cache access frequency. Here, we introduce two microarchitectural solutions to address this inefficiency. Our solutions rely on grouping write accesses and bypassing read accesses made to the same cache set. We reduce cache access frequency up to 55%.