A fast hardware-friendly motion estimation algorithm and its VLSI design for real time ultra high definition applications

In this paper the Low Density and Iterative Search (LD&IS) motion estimation algorithm, and it hardware design for real time ultra high definition applications are presented. The LD&IS is a fast hardware-friendly algorithm that can be divided into two main steps: a low density multipoint search and a central iterative evaluation. This combination provides an efficient way to evade from local minima falls and increasing the image quality, especially for high definition videos. The LD&IS reached HD an average PSNR gain of 1.40 dB when compared to the Diamond Search algorithm high resolution videos. The LD&IS presents an increasing in the number of compared blocks, however, its performance could be similar to the DS algorithm for hardware implementation. There are no data dependences at the low density multipoint search step of the LD&IS algorithm, allowing the free exploration of the parallelism. The LD&IS architecture was designed targeting real time processing for QFHD videos. The architecture was described in VHDL and synthesized for an Altera Stratix 4 FPGA. Synthesis results show that the LD&IS architecture is capable to process QFHD videos in real time with a good trade-off between quality and hardware resources utilization.