A circuit synthesis algorithm for coarse grained dynamic reconfigurable circuits

Reconfigurable Computing (RC) is a promising paradigm that addresses the conflicting hardware design requirements of high performance and area efficiency. Coarsegrained architecture RC (CGA-RC) operates at the word level of granularity and exhibits better power and performance than fine-grained architectures. High level synthesis for Coarse-Grained Architecture Reconfigurable Computing (CGA-RC) devices from high-level descriptions is urgently needed to improve design efficiency. To realize this, it is also necessary to achieve both good performance and high PE (Processing Element) utilization automatically for all applications. In this paper, we address this issue by focusing on nested loop pipelining and hierarchical allocation of PEs and propose an algorithm to generate CGA-RC circuit configurations automatically. The methodology is compared with other methods to evaluate its performance.