Low cost and high throughput FME interpolation for the HEVC emerging video coding standard

The new demands for high resolution digital video applications are pushing the development of new techniques in the video coding area. This paper presents the hardware design of the sub-pixel interpolator for the Fractional Motion Estimation algorithm defined by the HEVC emerging standard. Based on evaluations using the HEVC reference software, a strategy was defined to be used in the architectural design. The designed architecture was described in VHDL and synthesized for Altera FPGAs. The hardware designed presents interesting results in terms of performance, being able to process QFHD videos (3840×2160 pixels) in real time.